The subject system and method are generally directed to an optimized timing recovery system for a receiver which employs digital receiver equalization to guard against the effects of intersymbol interference (ISI). More specifically, the subject system and method are directed to carrying out accurate phase recovery for such systems, and doing so in a manner which adaptively mitigates the potential corrupting effects of the digital receiver equalization thereon.
In various digital systems, signals are generally transmitted from a transmitter to a receiver through a transmission channel established therebetween. The channel may be any suitable medium which links the transmitter to the receiver, and may be established in wired or wireless manner. Depending on the particular application, the channel may be quite lossy, especially at high data transmission speeds (for example, on the order of 8 Gigabits/second or even higher). The transmission losses due to interference, attenuation, delay, and the like in the channel may have considerable detrimental effect on the transmitted signal by the time it reaches the receiver. In digital systems, such channel transmission effects cause sufficient amplitude and phase distortion to cause intersymbol interference (ISI) in the signal received at the receiver. That is, a pulse or other symbol representing the logic state of one data bit may be effectively ‘smeared’ to the degree that it contributes to the content of one or more succeeding bits. ISI generally includes the distortion of succeeding bits (called post-cursor ISI) and preceding bits (called pre-cursor ISI).
To guard against such detrimental effects, in particular post-cursor ISI, receiver systems heretofore known employ such digital receiver equalization measures as decision feedback equalization (DFE) to correct the received data by adaptive scaling. In digital receiver systems, however, some form of timing recovery, such as in clock and data recovery (CDR) blocks, is typically performed. An unintended consequence of digital equalization is that the corrective scaling may in certain instances corrupt phase detection during timing recovery. The greater the required equalization correction, the greater the likelihood of corrupting phase detection.
Approaches have been taken in the art to minimize the detrimental effect of DFE on timing recovery. These include the following:                Designing the receiver with sufficiently complex front end hardware that the required equalization corrections are minimized in degree;        Employing baud rate timing recovery that inefficiently avoids the use of timing information at the edges of received symbols; and,        Using a separate, dedicated clock path for frequency recovery followed by a phase interpolator to adjust phase, such that phase interpolators are employed in both clock recovery (frequency lock) and the phase lock paths. But each approach has notable drawbacks which limits its use in many applications, prohibitively so in some applications.        
There is therefore a need for a timing recovery system for a receiver employing digital equalization which mitigates potential timing corruption due to that digital equalization of the received signal. There is a need for such timing recovery system wherein the potential corruption is selectively mitigated on an as needed basis for system simplicity and economy.